Stacked ferroelectric memory devices, methods of manufacturing the same, ferroelectric memory circuits and methods of driving the same

ABSTRACT

A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 USC § 119 to Korean PatentApplication No. 2006-14639 filed on Feb. 15, 2006, the contents of whichare herein incorporated by reference in their entirety for all purposes.

BACKGROUND

1. Technical Field

Example embodiments of the invention relate to stacked ferroelectricmemory devices, methods of manufacturing the stacked ferroelectricmemory devices, ferroelectric memory circuits and methods of driving theferroelectric memory circuits. More particularly, example embodiments ofthe invention relate to stacked ferroelectric memory devices in which arandom access operation is available and data is quickly readablewithout destroying data, methods of manufacturing the stackedferroelectric memory devices, ferroelectric memory circuits in which arandom access operation is available and data is quickly readablewithout destroying data, and methods of driving the ferroelectric memorycircuits.

2. Description of the Related Art

Recently, various kinds of non-volatile memory devices have been studiedas a next-generation memory device for replacing dynamic random accessmemory (DRAM) devices. The non-volatile memory devices have been studiedwith a goal of achieving a high storage capacity, a high response speedand a low power consumption architecture. Examples of thenext-generation memory devices are magnetic random access memory (MRAM)devices, ferroelectric random access memory (FRAM) devices, phase-changerandom access memory (PRAM) devices, resistive random access memory(RRAM) devices, etc. The FRAM devices have an advantage that data in theFRAM devices is not volatile. Additionally, the FRAM devices have otheradvantages such as a high processing speed and a low power consumptionarchitecture, which make the FRAM devices desirable for furtherresearch.

The FRAM devices have a ferroelectric transistor or a ferroelectriccapacitor including a ferroelectric material serving as a memory, orstorage, member in a unit cell. The ferroelectric material hashysteretic characteristics due to its spontaneous polarization. The unitcell of the FRAM devices may be implemented to have various structuressuch as a 1T1C structure consisting of one selection transistor and onecapacitor or a 2T2C structure consisting of two selection transistorsand two capacitors. Additionally, the unit cell of the FRAM devices mayhave a 1T structure consisting of one selection transistor.

When the FRAM devices have a unit cell of the 1T1C structure or the 2T2Cstructure, the FRAM devices perform a destructive readout (DRO)operation and a write-back operation after reading data, thereby slowingdown the speed of reading data. Additionally, at least one transistorand one capacitor are needed in the unit cell so that an area occupiedby the unit cell may be increased relative to other structures.

When the FRAM devices have a unit cell of the 1T structure, data may bedetermined by a fluctuation in the size of the drain current flowing ina channel region of the transistor that varies according to thepolarization direction of a ferroelectric layer used as a gateinsulation layer. The FRAM devices having the unit cell of the 1Tstructure may read data without destroying data, i.e., the FRAM devicesperform a non-destructive readout (NDRO) operation so that reading datamay be completed very quickly. Additionally, the degree of integrationmay be increased relative to other structures because only oneferroelectric transistor is needed in the unit cell. However, the FRAMdevices having the unit cell of the 1T structure may have a significantdisadvantage over other structures in that a read/write operation isperformed by pages or blocks because a random access operation is notavailable in the above FRAM devices.

Therefore, there have been demands for non-volatile memory devices whichare capable of performing a fast reading operation and a random accessoperation, i.e., an operation that selectively reads/writes data on aselected address, and also have a high degree of integration.

SUMMARY

Example embodiments of the invention provide stacked ferroelectricmemory devices having a high degree of integration in which anon-destructive readout (NDRO) operation and a random access operationare available.

Other example embodiments of the invention provide methods ofmanufacturing the stacked ferroelectric memory devices having a highdegree of integration in which an NDRO operation and a random accessoperation are available.

Still other example embodiments of the invention provide ferroelectricmemory circuits in which an NDRO operation and a random access operationare available and at least two data may be stored in a unit cell.

Example embodiments of the invention also provide methods of driving theferroelectric memory circuits in which an NDRO operation and a randomaccess operation are available and at least two data may be stored inthe unit cell.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the invention will becomemore apparent by describing detailed example embodiments thereof withreference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram illustrating a ferroelectric memory devicein accordance with example embodiments of the invention;

FIG. 2 is a cross-sectional view illustrating a ferroelectric transistorof FIG. 1, which may store multi-level information;

FIG. 3 shows polarization characteristics of a ferroelectric transistorwhen data “1” and “1” is written to the ferroelectric transistor;

FIG. 4 shows polarization characteristics of a ferroelectric transistorwhen data “0” and “0” is written to the ferroelectric transistor;

FIG. 5 shows polarization characteristics of a ferroelectric transistorwhen data “1” and “0” is written to the ferroelectric transistor;

FIG. 6 shows polarization characteristics of a ferroelectric transistorwhen data “0” and “1” is written to the ferroelectric transistor;

FIG. 7 is a cross-sectional view illustrating a ferroelectric memorydevice in accordance with example embodiments of the invention;

FIG. 8 is a top plan view of a structure including elements formed underthe active pattern in FIG. 7;

FIG. 9 is a top plan view of a structure including elements formed underthe first data line over the active pattern in FIG. 7; and

FIGS. 10 to 18 are cross-sectional views illustrating a method ofmanufacturing the ferroelectric memory device of FIG. 7 in accordancewith some example embodiments of the invention.

DETAILED DESCRIPTION

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which example embodiments of the invention areshown. The invention may, however, be embodied in many different formsand should not be construed as limited to the example embodiments setforth herein. Rather, these example embodiments are provided so thatthis disclosure will be thorough and complete, and will fully convey thescope of the invention to those skilled in the art. In the drawings, thesizes and relative sizes of layers and regions may be exaggerated forclarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. Like numerals refer to likeelements throughout. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms arc intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularexample embodiments only and is not intended to be limiting of theinvention. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises” and/or “comprising,” when used in this specification,specify the presence of stated features, integers, steps, operations,elements, and/or components, but do not preclude the presence oraddition of one or more other features, integers, steps, operations,elements, components, and/or groups thereof.

Example embodiments of the invention are described herein with referenceto cross-section illustrations that are schematic illustrations ofidealized example embodiments (and intermediate structures) of theinvention. As such, variations from the shapes of the illustrations as aresult, for example, of manufacturing techniques and/or tolerances, areto be expected. Thus, example embodiments of the invention should not beconstrued as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes that result, for example,from manufacturing tolerances. For example, an implanted regionillustrated as a rectangle will, typically, have rounded or curvedfeatures and/or a gradient of implant concentration at its edges ratherthan a binary change from implanted to non-implanted region. Likewise, aburied region formed by implantation may result in some implantation inthe region between the buried region and the surface through which theimplantation takes place. Thus, the regions illustrated in the figuresare schematic in nature and their shapes are not intended to illustratethe actual shape of a region of a device and are not intended to limitthe scope of the invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Hereinafter, example embodiments of the invention will be explained indetail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram illustrating a ferroelectric memory devicein accordance with example embodiments of the invention. As shown inFIG. 1, a cell array of the ferroelectric memory device includes eightunit cells. Each unit cell includes a selection transistor and aferroelectric transistor. For example, each of the elements that aredisposed at areas indicated as a reference numeral 35 and a referencenumeral 45 functions as one of the unit cells, i.e., a first unit celland a second unit cell, respectively.

Referring to FIG. 1, a first string 12 having selection transistors 10,30, 40, and 50 that are connected in series with each other is prepared.Reference numerals 10, 30, 40 and 50 indicate some of the selectiontransistors, however, the rest of the eight selection transistors inFIG. 1 are not indicated with reference numerals in order to simplifythe circuit diagram. Each of the selection transistors 10, 30, 40, and50 includes a first gate structure, a first source region and a firstdrain region. Metal-oxide-semiconductor (MOS) transistors may beemployed as the above-mentioned selection transistors. That is, thefirst gate structure included in each of the selection transistors 10,30, 40 and 50 has a structure in which a gate insulation layer patternand a conductive pattern are sequentially stacked on a substrate. In anexample embodiment of the invention, a plurality of the first strings 12is formed in the cell array of a semiconductor memory device, and two ofthe first strings 12 are shown in FIG. 1. Each of the first strings 12may be disposed in parallel to one another.

The ferroelectric memory device includes a plurality of word lines WL1,WL2, WL3 and WL4, and each of the word lines WL1, WL2, WL3 and WL4 iselectrically connected to some of the first gate structures. The wordlines WL1, WL2, WL3 and WL4 are disposed in a first direction D1substantially perpendicular to a second direction D2, i.e., an extensiondirection of the first strings 12. The gate structures of the selectiontransistors 10, 30, 40 and 50, which are electrically connected to theword lines WL1, WL2, WL3 and WL4, respectively, may be turned on orturned off by applying a voltage above a threshold voltage to the wordlines WL1, WL2, WL3 and WL4.

The ferroelectric memory device includes bit lines BL1 and BL2, whichare electrically connected to the first source regions and extend in thesecond direction D2. That is, the bit lines BL1 and BL2 extend toconnect each of the first source regions of the selection transistors10, 30, 40 and 50. Thus, one of the word lines WL1, WL2, WL3 and WL4 andone of the bit lines BL1 and BL2 are enabled so that one of theselection transistors 10, 30, 40 and 50, which is disposed at aninterface between the enabled word line and the enabled bit line, may beturned on. Data may be selectively read from or written into one offerroelectric transistors 14, 32, 42 and 54, which is electricallyconnected to the turned-on transistor, i.e. the selection transistor 10,30, 40 or 50 that has been turned on by the enabled word line and bitline combination.

The ferroelectric memory device includes a second string 16 having aplurality of ferroelectric transistors each of which includes a secondgate structure, a second source region and a second drain region.Reference numerals 14, 32, 42 and 54 indicate some of the ferroelectrictransistors, however, the rest of the eight ferroelectric transistors inFIG. 1 are not indicated with reference numerals in order to simplifythe circuit diagram. The second gate structure included in each of theferroelectric transistors 14, 32, 42 and 54 has a structure in which aferroelectric pattern and a conductive pattern are sequentially stackedon the substrate. In an example embodiment of the invention, a pluralityof the second strings 16 is formed in the cell array of a semiconductormemory device, and two of the second strings 16 are shown in FIG. 1.Each of the second strings 16 may be disposed in parallel to oneanother. The ferroelectric pattern has characteristics that thepolarization direction of the ferroelectric pattern changes according toan external voltage applied to the ferroelectric pattern.

In an example embodiment of the invention, the ferroelectric transistors14, 32, 42 and 54 may be operable to store multi-level information.

FIG. 2 is a cross-sectional view illustrating the ferroelectrictransistor of FIG. 1, which may store multi-level information.

In an example embodiment of the invention, a second source region 20 anda second drain region 22 of the ferroelectric transistor 14 is formed tobe overlapped by side portions of the second gate structure 28 as shownin FIG. 2. The second gate structure 28 has a structure in which aferroelectric pattern 24 and an electrode 26 are sequentially stacked ona substrate 19. In an example embodiment of the invention, the substrate19 is a bulk substrate and the electrode 26 has a plate shape. Thesecond gate structure 28 may have three regions including a first region29 a, a second region 29 b and a third region 29 c. The second gatestructure 28 may overlap the second source region 20 at the first region29 a. The second gate structure 28 may overlap a channel region, whichis disposed between the second source region 20 and the second drainregion 22 of the substrate 19, at the second region 29 b. The secondgate structure 28 may overlap the second drain region 22 at the thirdregion 29 c.

Referring again to FIG. 1, the first drain regions of the selectiontransistors 10, 30, 40 and 50 are electrically connected to the secondsource regions of the ferroelectric transistors 14, 32, 42 and 54, eachof which corresponds to each of the selection transistors 10, 30, 40 and50, respectively, so that data may be selectively read from or writteninto the ferroelectric transistors 14, 32, 42 and 54 using the selectiontransistors 10, 30, 40 and 50.

The ferroelectric memory device includes plate electrode lines PL1, PL2,PL3 and PL4 electrically connecting each of the second gate structuresdisposed in the first direction D1. A voltage difference between thesecond gate structure and the channel region or a voltage differencebetween the second gate structure and the second source or drain regionmay be controlled by applying a predetermined voltage to the plateelectrode lines PL1, PL2, PL3 and PL4. Additionally, a polarizationdirection of the ferroelectric pattern may be changed by controlling thevoltage differences.

The ferroelectric memory device includes first data lines DL1, DL2 andDL3 electrically connected to the second drain regions. Each of thefirst data lines DL1, DL2 and DL3 extends in the first direction D1.

Additionally, the ferroelectric memory device includes second data linesDL_1, DL_2 and DL_3 electrically connected to the channel regions. Eachof the second data lines DL_1, DL_2 and DL_3 extends in the seconddirection D2.

Thus, data may be selectively read from or written into theferroelectric transistor electrically connected to the turned-onselection transistor by driving one of the plate electrode lines PL1,PL2, PL3 and PL4, one of the first data lines DL1, DL2 and DL3, and oneof the second data lines DL_1, DL_2 and DL_3, each of which isinterlocked with the turned-on selection transistor.

Hereinafter, a method of performing read/write operations in the unitcells of the ferroelectric memory device shown in FIG. 1 is illustratedwith reference to FIG. 1 and FIGS. 3 to 6. Specifically, when at leasttwo data may be simultaneously recorded in one unit cell, a method ofperforming read/write operations for the at least two data recorded inone unit cell of the ferroelectric memory device will be illustrated.

First, a method of writing data into the unit cells of the ferroelectricmemory device is illustrated. In the present example embodiment, data iswritten into the first unit cell 35 of the ferroelectric memory devicein FIG. 1 for convenience of explanation.

Writing Data “1” and “1”

In an example embodiment of the invention, data “1” and “1” are writteninto the first unit cell 35 by inducing a negative charge into a channelregion including a first portion of the channel region adjacent to thesecond source region and a third portion of the channel region adjacentto the second drain region.

The selection transistor 30 included in the first unit cell 35 isdriven. Particularly, a high signal is applied to the word line WL2electrically connected to the selection transistor 30, thereby turningon the first gate structures electrically connected to the word lineWL2.

A low signal is applied to the bit line BL1 electrically connected tothe selection transistor 30. When the low signal is applied to the bitline BL1, no voltage is applied to the second source region 20 of theferroelectric transistor 32 through the first drain region of theselection transistor 30.

A low signal, which is a signal substantially the same as that appliedto the bit line BL1, is applied to each of the first data line DL2 andthe second data line DL_1 that are electrically connected to theferroelectric transistor 32 included in the first unit cell 35.

A high signal, which is a signal substantially opposite to that appliedto the bit line BL1, is applied to the second gate structure 28 throughthe plate line PL2.

FIG. 3 shows polarization characteristics of a ferroelectric transistorwhen data “1” and “1” is written to the ferroelectric transistor.

That is, when signals are applied to the ferroelectric transistor 32 asshown in FIG. 3, polarization occurs in the ferroelectric pattern 24according to hysteretic characteristics of the ferroelectric pattern 24.Thus, the negative charge may be induced to the channel region andremain in the channel region.

Writing Data “0” and “0”

In an example embodiment of the invention, data “0” and “0” are writteninto the first unit cell 35 by inducing a positive charge into thechannel region including the first portion of the channel regionadjacent to the second source region and the third portion of thechannel region adjacent to the second drain region.

The selection transistor 30 included in the first unit cell 35 isdriven. Particularly, a high signal is applied to the word line WL2electrically connected to the selection transistor 30, thereby turningon the first gate structures electrically connected to the word lineWL2.

A high signal is applied to the bit line BL1 electrically connected tothe selection transistor 30. When the high signal is applied to the bitline BL1, a voltage is applied to the second source region 20 of theferroelectric transistor 32 through the first drain region of theselection transistor 30.

A high signal, which is a signal substantially the same as that appliedto the bit line BL1, is applied to each of the first data line DL2 andthe second data line DL_1 that are electrically connected to theferroelectric transistor 32 included in the first unit cell 35.

A low signal, which is a signal substantially opposite to that appliedto the bit line BL1, is applied to the second gate structure 28 throughthe plate line PL2.

FIG. 4 shows polarization characteristics of a ferroelectric transistorwhen data “0” and “0” is written to the ferroelectric transistor.

When signals are applied to the ferroelectric transistor 32 as shown inFIG. 4, polarization occurs in the ferroelectric pattern 24 according tohysteretic characteristics of the ferroelectric pattern 24. Thus, thepositive charge may be induced to the channel region and remain in thechannel region.

Writing Data “1” and “0”

In an example embodiment of the invention, data “1” and “0” are writteninto the first unit cell 35 by inducing a negative charge into thechannel region including the third portion of the channel regionadjacent to the second drain region and by inducing a positive chargeinto the first portion of the channel region adjacent to the secondsource region.

The selection transistor 30 included in the first unit cell 35 isdriven. Particularly, a high signal is applied to the word line WL2electrically connected to the selection transistor 30, and the firstgate structures electrically connected to the word line WL2 are turnedon.

A low signal is applied to the bit line BL1 electrically connected tothe selection transistor 30. When the low signal is applied to the bitline BL1, no voltage is applied to the second source region 20 of theferroelectric transistor 32 through the first drain region of theselection transistor 30.

A low signal, which is a signal substantially the same as that appliedto the bit line BL1, is applied to each of the first data line DL2 andthe second data line DL_1 that are electrically connected to theferroelectric transistor 32 included in the first unit cell 35.

A high signal, which is a signal substantially opposite to that appliedto the bit line BL1, is applied to the second gate structure 28 throughthe plate line PL2.

Polarization characteristics of the ferroelectric transistor 32 as shownin FIG. 3 may occur when the ferroelectric memory device is operated bythe above processes.

A direction of the polarization in the first region 29 a of the secondgate structure 28 is then changed into a direction substantiallyopposite to the original direction.

Specifically, a high signal is applied to the bit line BL1. When thehigh signal is applied to the bit line BL1, a voltage is applied to thesecond source region 20 of the ferroelectric transistor 32 through thefirst drain region of the selection transistor 30. Additionally, a lowsignal, which is a signal substantially opposite to that applied to thebit line BL1, is applied to each of the second gate structure 28, thefirst data line DL2 and the second data line DL_1.

FIG. 5 shows polarization characteristics of a ferroelectric transistorwhen data “1” and “0” is written to the ferroelectric transistor.

As shown in FIG. 5, directions of the polarization in the second andthird regions 29 b and 29 c are not changed because voltages in thesecond and third regions 29 b and 29 c are not changed, whereas thedirection of the polarization in the first region 29 a of the secondgate structure 28 is changed into the direction substantially oppositeto the original direction.

Thus, a negative charge is induced into most portions of the channelregion, while a positive charge may be induced into the first portion ofthe channel region adjacent to the second source region so that adepletion region may be generated in the first portion of the channelregion.

Writing Data “0” and “1”

In an example embodiment of the invention, data “0” and “1” are writteninto the first unit cell 35 by inducing a positive charge into thechannel region except for the first portion of the channel regionadjacent to the second source region and the third portion of thechannel region adjacent to the second drain region, and by inducing anegative charge into the first portion of the channel region and thethird portion of the channel region.

The selection transistor 30 included in the first unit cell 35 isdriven. Particularly, a high signal is applied to the word line WL2electrically connected to the selection transistor 30, and the firstgate structures electrically connected to the word line WL2 are turnedon.

A high signal is applied to the bit line BL1 electrically connected tothe selection transistor 30. When the high signal is applied to the bitline BL1, a voltage is applied to the second source region 20 of theferroelectric transistor 32 through the first drain region of theselection transistor 30.

A high signal, which is a signal substantially the same as that appliedto the bit line BL1, is applied to each of the first data line DL2 andthe second data line DL_1 that are electrically connected to theferroelectric transistor 32 in the first unit cell 35.

A low signal, which is a signal substantially opposite to that appliedto the bit line BL1, is applied to the second gate structure 28 throughthe plate line PL2.

FIG. 4 illustrates polarization characteristics of the ferroelectrictransistor 32 when the ferroelectric memory device is operated by theabove processes.

Directions of the polarization in the first and third regions 29 a and29 c of the second gate structure 28 are then changed into directionssubstantially opposite to the original directions.

Specifically, a low signal is applied to the bit line BL1. When the lowsignal is applied to the bit line BL1, no voltage is applied to thesecond source region 20 of the ferroelectric transistor 32 through thefirst drain region of the selection transistor 30. Additionally, a lowsignal, which is a signal substantially the same as that applied to thebit line BL1, is applied to the first data line DL2.

Furthermore, a high signal, which is a signal substantially opposite tothat applied to the bit line BL1 and the first data line DL2, is appliedto each of the second data line DL_1 and the second gate structure 28.

FIG. 6 shows polarization characteristics of a ferroelectric transistorwhen data “0” and “1” is written to the ferroelectric transistor.

As shown in FIG. 6, directions of the polarization in the first andthird regions 29 a and 29 c are changed into the directionssubstantially opposite to the original directions because voltages inthe first and third regions 29 a and 29 c are changed, whereas thedirection of the polarization in the second region 29 b of the secondgate structure 28 remains the same.

Thus, a positive charge is induced into a central portion of the channelregion, whereas a negative charge may be induced into the first portionof the channel region adjacent to the second source region and the thirdportion of the channel region adjacent to the second drain region sothat a depletion region may be generated in the central portion of thechannel region.

As described above, a method of writing two data into one unit cell ofthe ferroelectric memory device has been illustrated, however, one datamay be written into one unit cell of the ferroelectric memory device.When one data is written into one unit cell, the second source region 20and the second drain region 22 of the ferroelectric transistor 32 do notneed to be formed and overlapped by the side portions of the second gatestructure 28 as shown in FIG. 2. Additionally, each of data “0” and data“1” may be written into the unit cell by a method substantially the sameas or similar to the above method for writing data “0” and “0” orwriting data “1” and “1.”

Hereinafter, a method of reading data recorded in the unit cells of theferroelectric memory device is illustrated. In the present exampleembodiment, data is read from the second unit cell 45 of theferroelectric memory device in FIG. 1 for convenience of explanation.

A selection transistor 40 included in the second unit cell 45 is turnedon. Particularly, a high signal is applied to each of the word line WL3and the bit line BL2, which are electrically connected to the selectiontransistor 40, so that the second unit cell 45 may be selected. Thus, areading voltage is applied to the second source region of theferroelectric transistor 42 through the first drain region of theselection transistor 40.

A drain current in the ferroelectric transistor 42 is established. Thatis, a current flowing through the first data line DL2 electricallyconnected to the second drain region of the ferroelectric transistor 42is established. No voltage is applied to the second gate structure 28while reading data.

The drain current may be varied according to data recorded in theferroelectric transistor 42.

For example, when data “1” and “1” are recorded in the unit cell, anegative charge is induced in the channel region so that a relativelylarge drain current may flow.

When data “1” and “0” are recorded in the unit cell, although a negativecharge is induced in most of the channel region, a depletion region isformed in a first portion of the channel region adjacent to the secondsource region, and thus a drain current slightly smaller than a draincurrent flowing when data “1” and “0” are recorded may flow.

When data “0” and “1” are recorded in the unit cell, a depletion regionis formed in a central portion of the channel region and a negativecharge is induced in the first portion of the channel region and thethird portion of the channel region adjacent to the second drain region,and thus a drain current slightly smaller than a drain current flowingwhen data “1” and “0” are recorded may flow.

When data “0” and “0” are recorded in the unit cell, a positive chargeis induced in the channel region, and thus a drain current that is thesmallest of the above-mentioned four cases may flow.

That is, the magnitude of the drain current Id that flows in theferroelectric transistor varies according to data recorded in the unitcell as follows:

Id (1, 1 while reading data)>Id (1, 0 while reading data)>Id (0, 1 whilereading data)>Id (0, 0 while reading data).

Data may be read from the unit cell by comparing the drain current thatactually flows to a reference current.

Particularly, when the drain current is determined to be larger than afirst reference current Iref1, data “1” and “1” may be read. When thedrain current is determined to be smaller than the first referencecurrent Iref1 but larger than a second reference current Iref2, data “1”and “0” are read. When the drain current is determined to be smallerthan the second reference current Iref2 but larger than a thirdreference current Iref3, data “0” and “1” are read. When the draincurrent is determined to be smaller than the third reference currentIref3, data “0” and “0” are read.

A pulse signal larger than a breakdown voltage is not applied betweenthe second gate structure 28 and the second source region 20, betweenthe second gate structure 28 and the second drain region 22, or betweenthe second gate structure 28 and the substrate 19 because a voltage isnot applied to the second gate structure 28 of the ferroelectrictransistor 42 while reading data. Thus, data stored in the unit cell mayremain even after the data is read. As a result, the ferroelectricmemory device may have characteristics such as non-volatility andnon-destructive readout (NDRO).

Additionally, after a unit cell is selected by driving the bit line BL2and the word line WL3, a desired data may be written into or read fromthe selected unit cell.

FIG. 7 is a cross-sectional view illustrating a ferroelectric memorydevice in accordance with example embodiments of the invention, FIG. 8is a top plan view of a structure including elements formed under theactive pattern in FIG. 7, and FIG. 9 is a top plan view of a structureincluding elements formed under the first data line over the activepattern.

An area “C” in FIG. 7 may serve as a unit cell in the ferroelectricmemory device.

Referring to FIGS. 7 and 8, an active region 100 a and an isolationregion (not shown) are formed in a substrate 100. The active region 100a may have a linear shape extending in a first direction.

A plurality of selection transistors each of which includes a first gatestructure 108, a first impurity region 112 and a second impurity region114 is formed on the substrate 100. The first gate structure 108 has agate insulation layer 102, a first gate electrode 104 and a first hardmask 106 that are sequentially stacked on the substrate 100. A firstspacer 110 may be formed on a sidewall of the first gate structure 108.The first spacer 110 may include silicon nitride.

Each of the first and second impurity regions 112 and 114 is formed atan upper portion of the substrate 100 adjacent to the first gatestructure 108, and may serve as a source region or a drain region. Thefirst gate electrode 104 included in the first gate structure 108 mayhave a linear shape extending in a second direction substantiallyperpendicular to the first direction. Thus, a plurality of the firstgate electrodes 104 may serve as a word line.

Each of the first and second impurity regions 112 and 114 may serve as acommon source region or a common drain region of two adjacent selectiontransistors. The selection transistors may be connected in series.

A first insulating interlayer 116 is formed on the substrate 100 tocover the selection transistors. A plurality of first openings 117 isformed through the first insulating interlayer to partially expose thefirst impurity region 112.

A plurality of bit line structures 122 is formed on or over thesubstrate 100 to be electrically connected to the first impurity region112. Particularly, each of the bit line structures 122 includes a bitline pad 118 and a bit line 120. The bit line pad 118 is formed on thesubstrate 100 to fill up one of the first openings 117. The bit line pad118 may include a conductive material. The bit line 120 is formed on thefirst insulating interlayer 116 to be connected to the bit line pad 118.The bit line 120 may have a linear shape extending in the firstdirection.

A second insulating interlayer 124 is formed on the first insulatinginterlayer 116 to cover the bit line structures 122. A plurality ofsecond openings 126 is formed through the first and second insulatinginterlayers 116 and 124 to partially expose the second impurity region114.

A plurality of plugs 128 is formed on the substrate 100 to fill up thesecond openings 126. The plugs 128 may include single crystallinesilicon. Each of the plugs 128 is formed through the first and secondinsulating interlayers 116 and 124 and has a height greater than thoseof the bit line structures 122. The plugs 128 may be formed by aselective epitaxial growth (SEG) process using the substrate 100 as aseed. The plugs 128 are doped with impurities having substantially thesame type as those doped in the second impurity region 114, and thus theplugs 128 are electrically connected to the second impurity region 114.

As shown in FIG. 7, one second impurity region 114 may serve as a commondrain region of two adjacent selection transistors, and thus one of theplugs 128 electrically connected to the second impurity region 114 maytransfer signals from the two adjacent selection transistors to otherelements.

Hereinafter, elements formed on or over the plugs 128 are illustrated.

Referring to FIGS. 7 and 9, a plurality of active patterns 130 is formedon the second insulating interlayer 124 to make contact with the plugs128. The active patterns 130 may include single crystalline silicon.Each of the active patterns 130 may serve as an active region forforming a ferroelectric transistor. In an example embodiment of theinvention, the ferroelectric transistor is formed to be opposite to theselection transistor. Each of the active patterns 130 may have a linearshape extending in the first direction.

A plurality of the ferroelectric transistors is formed on the activepatterns 130.

Each of the ferroelectric transistors has a second gate structure 138including a ferroelectric layer pattern 132, a second gate electrode 134and a second hard mask 136 that are sequentially stacked on the activepatterns 130, a third impurity region 142 and a fourth impurity region144.

The second gate structure 138 may have a structure such as ametal-ferroelectric-silicon (MFS) structure, ametal-ferroelectric-metal-silicon (MFMS) structure, ametal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure,etc.

A second spacer 140 may be further formed on a sidewall of the secondgate structure 138. The second spacer 140 may include silicon nitride.

Alternatively, the second spacer 140 may include a stacked structure inwhich an aluminum oxide layer and a silicon nitride layer aresequentially stacked, thereby preventing degradation of theferroelectric layer pattern 132.

The second gate electrode 134 may have a linear shape extending in thesecond direction substantially perpendicular to the first direction.Thus, the second gate electrode 134 may serve not only as a gateelectrode of the ferroelectric transistor but also as a gate electrodeline connecting a plurality of the gate electrodes to one another.

The ferroelectric layer pattern 132 may include a material in whichpolarization may occur according to an external voltage. For example,the ferroelectric layer pattern 132 may include PZT [Pb(Zr, Ti)O₃], SBT[Sr(Bi, Ti)O₃], BLT [Bi(La, Ti)O₃], PLZT [Pb(La, Zr)TiO₃], BST[Bi(Sr,Ti)O₃], etc. When the ferroelectric layer pattern 132 includes PZT,zirconium and titanium may be included at a ratio by weight of about25:75 to about 40:60. Additionally, the ferroelectric layer pattern 132may include PZT, SBT, BLT, PLZT, BST, etc., doped with potassium,lanthanum, manganese, bismuth, etc.

Each of the third and fourth impurity regions 142 and 144 may serve as asource region or a drain region of the ferroelectric transistor, and isformed at an upper portion of each of the active patterns 130 adjacentto the second gate structure 138.

In an example embodiment of the invention, each of the third and fourthimpurity regions 142 and 144 may serve as a common source region or acommon drain region of two adjacent ferroelectric transistors. Theferroelectric transistors may be connected in series.

The third and fourth impurity regions 142 and 144 are doped withimpurities having substantially the same type as those doped in thefirst and second impurity regions 112 and 114.

In some example embodiments of the present invention, the third andfourth impurity regions 142 and 144 are formed to be overlapped by sideportions of the second gate structure 138 so that at least two data maybe simultaneously written into or read from one ferroelectrictransistor. Hereinafter, a first portion of the ferroelectric layerpattern 132 overlapping the third impurity region 142 is referred to asa first region, a second portion of the ferroelectric layer pattern 132overlapping a channel region is referred to as a second region, and athird portion of the ferroelectric layer pattern 132 overlapping thefourth impurity region 144 is referred to as a third region.

A fifth impurity region 146 is formed in each of the active patterns 130to electrically connect the third impurity region 142 to each of theplugs 128. The fifth impurity region 146 is doped with impurities havingsubstantially the same type as those doped in the second impurity region114. Thus, the third impurity region 142 may be electrically connectedto the second impurity region 114 through each of the plugs 128 and thefifth impurity region 146.

A third insulating interlayer 148 is formed on the active patterns 130to cover the ferroelectric transistors. A plurality of third openings150 is formed through the third insulating interlayer 148 to partiallyexpose the fourth impurity region 144.

A plurality of first data line structures 156 is formed on or over theactive patterns 130 to be electrically connected to the fourth impurityregion 144. Particularly, each of the first data line structures 156includes a first data line pad 152 and a first data line 154. The firstdata line pad 152 is formed on the active patterns 130 to fill up thethird openings 150. The first data line pad 152 may include a conductivematerial. The first data line 154 is formed on the third insulatinginterlayer 148 to make contact with the first data line pad 152.

A fourth insulating interlayer 160 is formed on the third insulatinginterlayer 148 to cover the first data line structures 156. A seconddata line structure 168 is formed on or over the active patterns 130. Inan example embodiment of the present invention, the second data linestructure 168 is connected to end portions of the active patterns 130.

Particularly, a fourth opening 162 is formed through the third andfourth insulating interlayers 148 and 160 to partially expose the activepatterns 130. In an example embodiment of the present invention, twofourth openings 162 are formed to expose the end portions of the activepatterns 130. The second data line structure 168 includes a second dataline pad 164 and a second data line 166. The second data line pad 164 isformed on the active patterns 130 to fill up the fourth opening 162. Inan example embodiment of the present invention, two second data linepads 164 are formed to fill up the two fourth openings 162 exposing theend portions of the active patterns 130.

In the ferroelectric memory device in accordance with some exampleembodiments of the present invention, the selection transistors and theferroelectric transistors are vertically stacked so that a horizontalarea for implementing a unit cell may be reduced. Particularly, the unitcell may have a size as small as 4F² (Here, “F” means a criticaldimension.)

Additionally, one selection transistor and one ferroelectric transistorare included in one unit cell so that the ferroelectric memory devicemay perform a random access operation and have NDRO characteristics.

FIGS. 10 to 18 are cross-sectional views illustrating a method ofmanufacturing the ferroelectric memory device of FIG. 7 in accordancewith some example embodiments of the present invention.

Referring to FIG. 10, a substrate 100 is prepared. The substrate 100 mayinclude single crystalline silicon. An upper portion of the substrate100 is removed by an etching process to form a trench (not shown). Thetrench may be formed to have a linear shape extending in a firstdirection. An insulating material is filled into the trench to form anisolation layer. Thus, an active region and a field region each of whichextends in the first direction are formed in the substrate 100.

A gate insulation layer is formed on the substrate 100. The gateinsulation layer may be formed by a thermal oxidation process or achemical vapor deposition (CVD) process.

A first conductive layer and a first hard mask layer are sequentiallyformed on the gate insulation layer. The first conductive layer may beformed using a doped polysilicon.

A first photoresist pattern (not shown) extending in a second directionsubstantially perpendicular to the first direction is formed on thefirst hard mask layer. The first hard mask layer is partially removed byan etching process using the first photoresist pattern as an etchingmask to form a first hard mask 106. The first hard mask 106 may have alinear shape extending in the second direction.

The first conductive layer and the gate insulation layer are partiallyremoved by an etching process using the first hard mask 106 as anetching mask to form a first gate electrode 104 and a gate insulationlayer pattern 102, respectively. Thus, a first gate structure 108including the gate insulation layer pattern 102, the first gateelectrode 104 and the first hard mask 106 that are sequentially stackedon the substrate 100 is formed. In an example embodiment of theinvention, a plurality of the first gate structures 108 is formed on thesubstrate 100.

A first spacer layer is formed on the substrate 100 to cover the firstgate structures 108. The first spacer layer may be formed using siliconnitride. The first spacer layer may be partially removed by an etch-backprocess, a chemical mechanical polishing (CMP) process, or a combinationprocess of etch-back and CMP to form a first spacer 110 on sidewalls ofthe first gate structures 108.

Impurities are implanted onto a top surface of the substrate 100, whichis not covered by the first gate structures 108. Thus, a first impurityregion 112 and a second impurity region 114 are formed at a top surfaceof the substrate 100 adjacent to the first gate structures 108.

A selection transistor may be formed on the substrate 100 by the aboveprocesses. In an example embodiment of the present invention, aplurality of the selection transistors is formed. Each of the first andsecond impurity regions 112 and 114 may serve as a common source regionor a common drain region of adjacent selection transistors. In anexample embodiment of the present invention, the first impurity region112 serves as a source region of the selection transistors and thesecond impurity region 114 serves as a drain region of the selectiontransistors.

Referring to FIG. 11, a first insulating layer 116 is formed on thesubstrate 100 to cover the first gate structures 108. The firstinsulating interlayer 116 may be formed using an oxide such asboro-phosphor silicate glass (BPSG), phosphor silicate glass (PSG),spin-on-glass (SOG), tetraethylorthosilicate (TEOS), plasma-enhancedtetraethylorthosilicate (PE-TEOS), undoped silicate glass (USG),high-density plasma chemical vapor deposition (HDP-CVD) oxide, etc. Thefirst insulating interlayer 116 may be formed by a CVD process, aplasma-enhanced chemical vapor deposition (PECVD) process, ahigh-density plasma chemical vapor deposition (HDP-CVD) process or anatomic layer deposition (ALD) process.

A planarization process may be further performed on the first insulatinginterlayer 116. In an example embodiment of the present invention, whenperforming the planarization process, the first insulating interlayer116 may be partially removed by a CMP process and an additionalinsulation layer may be formed on the first insulating interlayer 116.

A second photoresist pattern (not shown) is formed on the firstinsulating interlayer 116. The second photoresist pattern may serve asan etching mask for forming a first opening 117, which partially exposesa first portion of the substrate 100.

The first insulating interlayer 116 is partially removed by an etchingprocess using the second photoresist pattern as an etching mask to formthe first opening 117 through the first insulating interlayer 116. In anexample embodiment of the invention, a plurality of the first openings117 is formed through the first insulating interlayer 116. The secondphotoresist pattern may be removed by an ashing process and/or astripping process.

A second conductive layer is formed on the substrate 100 to fill up thefirst opening 117. The second conductive layer may be formed using dopedpolysilicon, metal, etc.

The second conductive layer is polished until a top surface of the firstinsulating interlayer 116 is exposed to form a bit line pad 118 fillingup the first opening 117. In an example embodiment of the presentinvention, a plurality of the bit line pads 118 is formed in theplurality of the first openings 117. The second conductive layer may bepolished by an etch-back process, a CMP process, or a combinationprocess of etch-back and CMP.

A third conductive layer is formed on the first insulating interlayer116 and the bit line pad 118. The third conductive layer may bepatterned to form a bit line 120. The bit line 120 is electricallyconnected to the bit line pad 118. In an example embodiment of thepresent invention, a plurality of the bit lines 120 is formed to beelectrically connected to the plurality of the bit line pads 118.

Particularly, a barrier layer (not shown) and a tungsten layer (notshown) are sequentially deposited on the first insulating interlayer 116and the bit line pads 118 to form the third conductive layer. Thebarrier layer may be formed using titanium and titanium nitride.Additionally, a second hard mask layer (not shown) is formed on thethird conductive layer. After a third photoresist pattern (not shown) isformed on the second hard mask layer, the second hard mask layer ispatterned by an etching process using the third photoresist pattern asan etching mask to form a second hard mask (not shown). In an exampleembodiment of the present invention, the second hard mask may be formedto have a linear shape extending in the first direction. The thirdconductive layer is patterned by an etching process using the secondhard mask to form the bit lines 120. The second hard mask may be removedafterwards.

Thus, a bit line structure 122 including the bit line pad 118 and thebit line 120 is completed by the above processes. In an exampleembodiment of the present invention, a plurality of the bit linestructures 122 each of which includes the bit line pad 118 and the bitline 120 is formed.

Alternatively, the second conductive layer may be formed to fill up thefirst opening 117 and have a sufficiently greater height above the firstinsulating interlayer 116 to form the bit line 120. The secondconductive layer may be patterned by an etching process using the secondhard mask to form the bit line structure 122 including the bit line pad118 and the bit line 120 that are electrically connected to each other.In other words, the bit line pad 118 and the bit line 120 may be formedsubstantially simultaneously.

Referring to FIG. 12, a second insulating interlayer 124 is formed onthe first insulating interlayer 116 to cover the bit line structure 122.The second insulating interlayer 124 may be formed using an oxide suchas BPSG, PSG, SOG, TEOS, PE-TEOS, USG, HDP-CVD oxide, etc. The secondinsulating interlayer 124 may be formed by a CVD process, a PECVDprocess, a HDPCVD process or ALD process.

A planarization process may be further performed on the secondinsulating interlayer 124. Particularly, the second insulatinginterlayer 124 may be polished by a CMP process. Additionally, aninsulation layer may be further formed on the second insulatinginterlayer 124.

After a fourth photoresist pattern (not shown) is formed on the secondinsulating interlayer 124, the second insulating interlayer 124 andfirst insulating interlayer 116 are partially removed by an etchingprocess using the fourth photoresist pattern as an etching mask to forma second opening 126 partially exposing the second impurity region 114through the first and second insulating interlayers 116 and 124. In anexample embodiment of the present invention, a plurality of the secondopenings 126 is formed through the first and second insulatinginterlayers 116 and 124.

The fourth photoresist pattern may be removed by an ashing processand/or a stripping process.

Referring to FIG. 13, a plug 128 is formed on the substrate 100 to fillup the second opening 126. In an example embodiment of the presentinvention, a plurality of the plugs 128 is formed in the plurality ofthe second openings 126. In an example embodiment of the presentinvention, the plug 128 may be formed using single crystalline silicon.Single crystalline silicon may grow by an SEG process using the exposedsecond impurity region 114 as a seed to fill up the second opening 126.When single crystalline silicon grows, impurities having a highconcentration may be doped into the single crystalline silicon in-situ.The impurities may have substantially the same type as those doped inthe first and second impurity regions 112 and 114. Single crystallinesilicon may sufficiently grow to cover a top surface of the secondinsulating interlayer 124.

Hereinafter, a process for growing single crystalline silicon isdescribed in detail.

After performing a cleaning process for removing a native oxide layerfrom the exposed second impurity region 114, an SEG process isperformed.

When a process temperature is less than about 750° C., singlecrystalline silicon may not easily grow. When the process temperature ismore than about 1,250° C., controlling growth of single crystallinesilicon may not be easy. Thus, the SEG process is preferably performedat a temperature of about 750 to about 1,250° C., and more preferablyperformed at a temperature of about 800 to about 900° C.

A silicon source gas may serve as a reaction gas used in the SEGprocess. Examples of the silicon source gas may includetetrachlorosilane gas (SiCl₄), silane gas (SiH₄), dichlorosilane gas(SiH₂Cl₂), trichlorosilane gas (SiHCl₃), etc. These may be used alone orin a combination thereof. In an example embodiment of the presentinvention, tetrachlorosilane gas serves as the silicon source gas.

Single crystalline silicon grows by the above SEG process using thesilicon source gas to sufficiently fill up the second opening 126, andsingle crystalline silicon may grow on a top surface of the secondinsulating interlayer 124 adjacent to the second opening 126.

In an example embodiment of the present invention, a capping layer (notshown) is formed on the second insulating interlayer 124. The cappinglayer and a top portion of the plug 128, which is formed on the topsurface of the second insulating interlayer 124, are polished by a CMPprocess.

Thus, the plug 128 filling up the second opening 126 and having a heightsubstantially the same as that of the second insulating interlayer 124may be formed. Alternatively, the capping layer may not be formed inorder to simplify the process.

The second impurity region 114 electrically connected to the plug 128may serve as a drain region of two adjacent selection transistors. Thus,one plug 128 may serve as a common plug transferring signals of the twoadjacent selection transistors.

Referring to FIG. 14, a preliminary active layer is formed on the secondinsulating interlayer 124 and the plug 128. In an example embodiment ofthe present invention, the preliminary active layer is formed usingamorphous silicon.

In an example embodiment of the present invention, an active layer maybe formed from the preliminary active layer by transforming amorphoussilicon into single crystalline silicon. The plug 128 including singlecrystalline silicon may be used as a seed in the above process.

Single crystalline silicon may be formed from amorphous silicon by aheat treatment process. When a temperature is less than about 570° C.,transforming amorphous silicon into single crystalline silicon may notbe easy. When the temperature is more than about 650° C., controllingthe heat treatment process may not be easy. Thus, the heat treatmentprocess is preferably performed at a temperature of about 570 to about650° C., and more preferably performed at a temperature of about 600 toabout 620° C.

Alternatively, single crystalline silicon may be formed from amorphoussilicon by exposing the preliminary active layer to laser energy.

After forming a fifth photoresist pattern (not shown) on the activelayer, the active layer is patterned by an etching process using thefifth photoresist pattern as an etching mask to form an active pattern130 on the second insulating interlayer 124 and the plug 128. In anexample embodiment of the present invention, a plurality of the activepatterns 130 is formed on the second insulating interlayer 124 and theplug 128.

The active pattern 130 may serve as an upper active region for forming aferroelectric transistor. In an example embodiment of the presentinvention, the active pattern 130 has a linear shape extending in thefirst direction in which the active region formed at an upper portion ofthe substrate 100 extends. Additionally, the active pattern 130 may beformed to be opposite to the active region at the upper portion of thesubstrate 100.

After forming an insulation layer (not shown) on the second insulatinginterlayer 124 to sufficiently cover the active pattern 130, theinsulation layer is polished until a top surface of the active pattern130 is exposed. That is, when a plurality of the active patterns 130 isformed, the insulation layer may serve as an isolation layer between theactive patterns 130.

As illustrated with reference to FIGS. 13 and 14, in one exampleembodiment of the present invention, the preliminary active layerincluding amorphous silicon is transformed into the active layerincluding single crystalline silicon using the plug 128 as a seed. Theactive layer is patterned to form the active pattern 130 serving as theupper active region.

In another example embodiment of the present invention, the plug 128 andthe active pattern 130 including single crystalline silicon may beformed by a damascene process. Particularly, after forming the secondinsulating interlayer 124 to have a relatively large height, the secondinsulating interlayer 124 is partially removed to form a second opening126 for the plug 128 and a trench (not shown) for the active pattern130. Single crystalline silicon is grown by an SEG process using thesubstrate 100 as a seed to form a single crystalline silicon layer. Thesingle crystalline silicon layer may sufficiently fill up the secondopening 126 and the trench. The single crystalline silicon layer may bepolished until a top surface of the second insulating interlayer 124 isexposed. Thus, the plug 128 may be formed in the second opening 126, andthe active pattern 130 may be formed in the trench.

Referring to FIG. 15, a ferroelectric layer is formed on the activepattern 130 and the insulation layer.

The ferroelectric layer may be formed using a material in whichpolarization may occur according to an external voltage. For example,the ferroelectric layer pattern 132 may be formed using PZT, SBT, BLT,PLZT, BST, etc. When the ferroelectric layer includes PZT, zirconium andtitanium may be included at a ratio by weight of about 25:75 to about40:60. Additionally, the ferroelectric layer may be formed using PZT,SBT, BLT, PLZT, BST, etc., doped with potassium, lanthanum, manganese,bismuth, etc. The ferroelectric layer may be formed by an organo-metalchemical vapor deposition (OMCVD) process, a sol-gel process, an ALDprocess, etc.

A fourth conductive layer is formed on the ferroelectric layer. Thefourth conductive layer may be formed using a doped metal oxide and ametal. In an example embodiment of the present invention, the fourthconductive layer is formed to have a multi-layered structure in which afirst layer including strontium ruthenium oxide (SRO), strontiumtitanium oxide (STO), calcium ruthenium oxide (CRO), etc., each of whichis doped with a metal such as copper, lead, bismuth, etc. at about 2 toabout 5 percent by weight based on the total weight thereof, and asecond layer including a metal such as iridium, platinum, ruthenium,palladium, gold, etc., are sequentially stacked on the ferroelectriclayer.

A third hard mask layer is formed on the fourth conductive layer. Thethird hard mask layer is partially removed by a conventionalphotolithography process to form a third hard mask 136. The third hardmask 136 may be formed to have a linear shape extending in the seconddirection substantially perpendicular to the first direction. In anexample embodiment of the present invention, the third hard mask layer136 may be formed to be opposite to the first gate structure 108.

The fourth conductive layer and the ferroelectric layer are partiallyremoved by an etching process using the third hard mask 136 as anetching mask to form a second gate electrode 134 and a ferroelectriclayer pattern 132, respectively. Thus, a second gate structure 138including the ferroelectric layer pattern 132, the second gate electrode134 and the second hard mask 136 that are sequentially stacked on theactive pattern 130 is formed. The second gate structure 138 may have alinear shape extending in the second direction. Thus, the second gateelectrode 134 included in the second gate structure 138 may serve notonly as a gate electrode of the ferroelectric transistor but also as agate electrode line. In an example embodiment of the present invention,a plurality of the second gate structures 138 is formed on the activepattern 130.

Additionally, a metal layer or an insulation layer and a metal layer maybe further formed on the active pattern 130 prior to forming theferroelectric layer.

A second spacer layer is formed on the active pattern 130 to cover thesecond gate structure 138. The second spacer layer may be formed usingsilicon nitride. The second spacer layer is partially removed by ananisotropic etching process to form a second spacer 140 on a sidewall ofthe second gate structure 138.

Alternatively, an encapsulating barrier layer (EBL) may be furtherformed on the second spacer layer to reduce degradation of theferroelectric layer. The EBL may be formed using aluminum oxide. Thesecond spacer 140 may be formed by partially removing the EBL and theferroelectric layer.

Referring to FIG. 16, impurities are implanted into the active pattern130 using the second gate structure 138 as an implantation mask. A heattreatment process may be performed on the active pattern 130 to form athird impurity region 142 and a fourth impurity region 144 at a topsurface of the active pattern 130 adjacent to the second gate structure138. In an example embodiment of the invention, the impurities dopedinto the active pattern 130 may have substantially the same type asthose doped into the first and second impurity regions 112 and 114.

The ferroelectric transistor may be formed by the above processes. In anexample embodiment of the present invention, a plurality of theferroelectric transistors is formed to be connected to one another inseries. Each of the third and fourth impurity regions 142 and 144 mayserve as a source region or a drain region. In an example embodiment ofthe present invention, the third impurity region 142 may serve as thesource region of the ferroelectric transistor, and the fourth impurityregion 144 may serve as the drain region of the ferroelectrictransistor.

A sixth photoresist pattern (not shown) is formed on the active pattern130. The sixth photoresist pattern partially exposes a portion of theactive pattern 130. Impurities are implanted into the exposed portion ofthe active pattern 130 using the sixth photoresist pattern as animplantation mask. A heat treatment process is performed on the activepattern 130 to form a fifth impurity region 146, which may electricallyconnect the third impurity region 142 to the plug 128. When theimpurities are implanted into the portion of the active pattern 130, theimpurities are deeply implanted thereto, so that the fifth impurityregion 146 may make contact with both of the third impurity region 142and the plug 128. In an example embodiment of the present invention, theimpurities doped into the fifth impurity region 146 may havesubstantially the same type as those doped into the third impurityregion 142.

Thus, the drain region of the selection transistor may be electricallyconnected to the source region of the ferroelectric transistor throughthe plug 128 and the fifth impurity region 146.

Above, a process for forming the fifth impurity region 146 after formingthe third and fourth impurity regions 142 and 144 has been illustrated,however, the fifth impurity region 146 may also be formed prior toforming the third and fourth impurity regions 142 and 144.

Referring to FIG. 17, a third insulating interlayer 148 is formed on theactive pattern 130 to cover the ferroelectric transistor. The thirdinsulating interlayer 148 may be formed using an oxide such as BPSG,PSG, SOG, PE-TEOS, USG, HDP-CVD oxide, etc. The third insulatinginterlayer 148 may be formed by a CVD process, a PECVD process, an ALDprocess, etc.

The third insulating interlayer 148 is partially removed by aphotolithography process to form a third opening 150 through the thirdinsulating interlayer 148. The third opening 150 may partially exposethe fourth impurity region 144. In an example embodiment of the presentinvention, a plurality of the third openings 150 is formed through thethird insulating interlayer 148.

A fifth conductive layer is formed on the third insulating interlayer148 to fill up the third opening 150. The fifth conductive layer ispolished until a top surface of the third insulating interlayer 148 isexposed to form a first data line pad 152 filling up the third opening150. The fifth conductive layer may be polished by an etch-back process,a CMP process, or a combination process of etch-back and CMP. In anexample embodiment of the present invention, a plurality of the firstdata line pads 152 is formed in a plurality of the third openings 150.

A sixth conductive layer is formed on the third insulating interlayer148 and the first data line pad 152. The sixth conductive layer ispatterned to form a first data line 154 electrically connected to thefirst data line pad 152. The first data line 154 may be formed to have alinear shape extending in the second direction in which the second gatestructure 138 extends. In an example embodiment of the presentinvention, a plurality of the first data lines 154 is formed on thethird insulating interlayer 148 and a plurality of the first data linepads 152.

In an example embodiment of the present invention, a fourth hard mask(not shown) may be further formed on the first data line 154.

A first data line structure 156 including the first data line pad 152and the first data line 154 may be formed by the above processes.

In an example embodiment of the present invention, the fifth conductivelayer may be formed to fill up the third opening 150 and have asufficiently great height from the third insulating interlayer 148.After planarizing a top surface of the fifth conductive layer, the fifthconductive layer may be patterned by an etching process tosimultaneously form the first data line pad 152 and the first data line154 that are electrically connected to each other.

Referring to FIG. 18, a fourth insulating interlayer 160 is formed onthe third insulating interlayer 148 to cover the first data line 154.The fourth insulating interlayer 160 and the third insulating interlayer148 are partially removed by a photolithography process to form a fourthopening 162 through the third and fourth insulating interlayers 148 and160. The fourth opening 162 may partially expose the active pattern 130.In an example embodiment of the present invention, two fourth openings162 are formed to expose end portions of the active patterns 130.

A seventh conductive layer is formed on the active pattern 130 to fillup the fourth opening 162. The seventh conductive layer is planarizeduntil a top surface of the fourth insulating interlayer 160 is exposedto form a second data line pad 164 in the fourth opening 162. Theseventh conductive layer may be planarized by an etch-back process, aCMP process, or a combination process of etch-back and CMP. In anexample embodiment of the present invention, two second data line pads164 are formed to fill up the two fourth openings 162 exposing the endportions of the active patterns 130.

An eighth conductive layer is formed on the fourth insulating interlayer160 and the second data line pad 164. The eighth conductive layer ispatterned to form a second data line 166 electrically connected to thesecond data line pad 164. The second data line 166 may be formed to havea linear shape extending in the second direction in which the secondgate structure 138 extends. In an example embodiment of the presentinvention, a plurality of the second data lines 166 is formed on thefourth insulating interlayer 160 and the second data line pad 164.Additionally, a fifth hard mask (not shown) may be further formed on thesecond data line 154. A second data line structure 168 including thesecond data line pad 164 and the second data line 166 may be formed bythe above processes.

Alternatively, the seventh conductive layer may be formed to fill up thefourth opening 162 and have a sufficiently greater height above thefourth insulating interlayer 160 to allow formation of the second dataline 166. After planarizing a top surface of the seventh conductivelayer, the seventh conductive layer may be patterned by an etchingprocess to simultaneously form the second data line pad 164 and thesecond data line 166 that are electrically connected to each other.

A ferroelectric memory device including a selection transistor and aferroelectric transistor that are vertically stacked in a unit cell maybe formed by the above processes. The ferroelectric transistor is formedon an active pattern, which is formed over a substrate, so that ahorizontal area for the unit cell may be reduced.

According to some example embodiments of the invention, a ferroelectricmemory device may be manufactured having advantages such that datareading time is short without destroying data, and a random accessoperation, which means data is selectively read or written at a desiredaddress, is possible. Additionally, a unit cell of the ferroelectricmemory device may have a size as small as 4F² so that the ferroelectricmemory device may have a high degree of integration.

According to one aspect of the invention, there is provided a stackedferroelectric memory device. The stacked ferroelectric memory deviceincludes a plurality of selection transistors, a first insulatinginterlayer, a plurality of bit line structures, a second insulatinginterlayer, a plurality of plugs, a plurality of active patterns, and aplurality of ferroelectric transistors. The plurality of selectiontransistors is formed on a substrate. The selection transistors areconnected in series and each of the selection transistors includes afirst gate structure, a first impurity region and a second impurityregion. Each of the first and the second impurity regions serves as acommon source/drain region of adjacent selection transistors. The firstinsulating interlayer covers the selection transistors. The plurality ofbit line structures is electrically connected to the first impurityregions. The second insulating interlayer covers the bit linestructures. The plurality of plugs includes doped single crystallinesilicon and is formed through the first and the second insulatinginterlayers. Each of the plugs makes contact with the second impurityregion and has a height greater than those of the bit line structures.The plurality of active patterns is formed on the plugs and the secondinsulating interlayer. Each of the active patterns makes contact withthe plugs. The plurality of ferroelectric transistors is formed on theactive patterns. The ferroelectric transistors are connected in seriesand each of the ferroelectric transistors has a second gate structure, athird impurity region and a fourth impurity region. The second gatestructure includes a ferroelectric layer pattern and a conductivepattern that are sequentially stacked. Each of the third and the fourthimpurity regions serves as a common source/drain region of adjacentferroelectric transistors.

In an example embodiment of the invention, the second gate structure mayhave one of a metal-ferroelectric-silicon (MFS) structure, ametal-ferroelectric-metal-silicon (MFMS) structure and ametal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure.

In an example embodiment of the invention, the third and the fourthimpurity regions may be overlapped by side portions of the second gatestructure so that at least two polarization states may be stored thereinby the second gate structure.

In an example embodiment of the invention, a spacer layer includingsilicon nitride and an encapsulating barrier layer (EBL) includingaluminum oxide may be stacked on a sidewall of the second gate structureto reduce degradation of the ferroelectric layer pattern.

In an example embodiment of the invention, a fifth impurity region maybe formed in each of the active patterns to connect the third impurityregion to each of the plugs.

In an example embodiment of the invention, the stacked ferroelectricmemory device may further include a plurality of first data linestructures. Each of the first data line structures may be connected tothe fourth impurity region.

In an example embodiment of the invention, the stacked ferroelectricmemory device may further include a second data line structureelectrically connected to a channel region of each of the ferroelectrictransistors. The channel region may be disposed between the third andthe fourth impurity regions.

In an example embodiment of the invention, the substrate may include anactive region and an isolation region. The active region may have alinear shape extending in a first direction.

In an example embodiment of the invention, the first gate structure mayhave a linear shape extending in a second direction substantiallyperpendicular to the first direction.

In an example embodiment of the invention, each of the active patternsmay have a linear shape extending in the first direction and is oppositeto the active region.

In an example embodiment of the invention, the second gate structure mayhave a linear shape extending in the second direction substantiallyperpendicular to the first direction.

According to another aspect of the invention, there is provided a methodof manufacturing a stacked ferroelectric memory device. In the method ofmanufacturing the stacked ferroelectric memory device, a plurality ofselection transistors is formed on a substrate. The selectiontransistors are connected in series and each of the selectiontransistors includes a first gate structure, a first impurity region anda second impurity region. The first and the second impurity regions areformed at upper portions of the substrate adjacent to the first gatestructure. A first insulating interlayer is formed on the substrate tocover the selection transistors. A plurality of bit line structureselectrically connected to the first impurity regions is formed. A secondinsulating interlayer is formed on the first insulating interlayer tocover the bit line structures. A plurality of plugs is formed usingdoped single crystalline silicon through the first and the secondinsulating interlayers. Each of the plugs makes contact with the secondimpurity region and has a height greater than those of the bit linestructures. A plurality of active patterns is formed on the plugs andthe second insulating interlayer. Each of the active patterns makescontact with the plugs. A plurality of ferroelectric transistors isformed on the active patterns. The ferroelectric transistors areconnected in series and each of the ferroelectric transistors has asecond gate structure, a third impurity region and a fourth impurityregion. The second gate structure includes a ferroelectric layer patternand a conductive pattern that are sequentially stacked.

In an example embodiment of the invention, the second gate structure maybe formed to have one of an MFS structure, an MFMS structure and anMFMIS structure.

In an example embodiment of the invention, the third and the fourthimpurity regions may be formed to be overlapped by side portions of thesecond gate structure by an implantation process, so that at least twopolarization states may be stored therein by the second gate structure.

In an example embodiment of the invention, a spacer layer may be furtherformed using silicon nitride on the active patterns to cover the secondgate structures. An EBL may be further formed on sidewalls of the secondgate structures using aluminum oxide to reduce degradation of theferroelectric layer pattern. A plurality of spacers may be furtherformed on the sidewalls of the second gate structures by anisotropicallyetching the spacer layer and the EBL.

In an example embodiment of the invention, a trench extending in a firstdirection may be further formed on the substrate by partially etchingthe substrate. An active region and an isolation region of the substratemay be further formed by filling the trench with an insulating material.

In an example embodiment of the invention, the first gate structure maybe formed to extend in a second direction substantially perpendicular tothe first direction. Impurities may be implanted onto portions of thesubstrate, which is not covered by the first gate structure, to form afirst impurity region and a second impurity region, which are partiallyoverlapped by side portions of the first gate structure.

In an example embodiment of the invention, a fifth impurity region maybe further formed in each of the active patterns by an implantationprocess to connect the third impurity region to each of the plugs.

In an example embodiment of the invention, a third insulating interlayermay be further formed on the active patterns to cover the ferroelectrictransistors after forming the ferroelectric transistors. A plurality offirst data line structures, each of which includes a first data line padand a first data line, may be further formed. The first data line padmay be formed through the third insulating interlayer to make contactwith the fourth impurity region, and the first data line may beelectrically connected to the first data line pad.

In an example embodiment of the invention, a fourth insulatinginterlayer may be further formed on the fourth insulating interlayer. Aplurality of second data line structures, each of which includes asecond data line pad and a second data line, may be further formed.

The second data line pad may be formed through the third and the fourthinsulating interlayers to make contact with a channel region of each ofthe active pattern. The second data line may be electrically connectedto the second data line pad. The channel region may be disposed betweenthe third and fourth impurity regions.

In an example embodiment of the invention, when the active patterns areformed, a preliminary active layer may be formed on the plugs and thesecond insulating interlayer using amorphous silicon. An active layermay be formed from the preliminary active layer by transformingamorphous silicon into single crystalline silicon. The active patternsmay be formed by patterning the active layer and have a linear shapeextending in the first direction.

In an example embodiment of the invention, the second gate structure mayhave a linear shape extending in the second direction.

The above stacked ferroelectric memory device has a stacked structure inwhich selection transistors and ferroelectric transistors are verticallystacked in a unit cell so that the stacked ferroelectric transistordevice may have a high integration degree. Additionally, a random accessoperation is possible and data is quickly readable without destroyingdata, i.e., a non-destructive readout (NDRO) operation is possible, inthe stacked ferroelectric memory device.

According to still another aspect of the invention, there is aferroelectric memory circuit. The ferroelectric memory circuit includesa first string, a plurality of word lines, a plurality of bit lines, asecond string, a plurality of plate electrode lines, a plurality offirst data lines, and a plurality of second data lines. The first stringhas a plurality of selection transistors each of which includes a firstgate structure, a first source region and a first drain region. Theselection transistors are connected in series and the first stringextends in a first direction. The plurality of word lines connects thefirst gate structures disposed in a second direction substantiallyperpendicular to the first direction. The plurality of bit lines extendsin the first direction. The bit lines are connected to the first sourceregions. The second string has a plurality of ferroelectric transistors,each of which includes a second gate structure, a second source regionand a second drain region. The ferroelectric transistors are formed onan active pattern to be connected in series and the second stringextends in a third direction. The second source region and the seconddrain region are overlapped by side portions of the second gatestructure so that each of the ferroelectric transistors storesmulti-level information, and the second source region is electricallyconnected to a corresponding first drain region. The plurality of plateelectrode lines connects between the second gate structures disposed ina fourth direction substantially perpendicular to the third direction.The plurality of first data lines is electrically connected to thesecond drain region. The plurality of second data lines is electricallyconnected to the active pattern.

In a method of driving a semiconductor device including the aboveferroelectric memory circuit, in one example embodiment of theinvention, a polarization direction may be recorded in each of a firstregion, a second region and a third region by turning on the selectiontransistor and applying a predetermined voltage to each of the secondgate structure, the second source region and the second drain region.The second source region may be overlapped by the first region of thesecond gate structure, a channel region disposed between the secondsource region and the second drain region may be overlapped by thesecond region, and the second drain region may be overlapped by thethird region. Two data may be read from one ferroelectric transistor byturning on the selection transistor and measuring a drain current of theferroelectric transistor. The drain current may vary according to thepolarization direction of each region of the second gate structure.

In an example embodiment of the invention, when the polarizationdirections in the second and the third regions are recorded to bedifferent from that of the first region, substantially the samepolarization directions may be recorded in each of the first, the secondand the third regions, and the polarization direction in the firstregion may be changed while recording the polarization direction.

In an example embodiment of the invention, when the polarizationdirections in the first and the third regions are recorded to bedifferent from that of the second region, substantially the samepolarization directions may be recorded in each of the first, the secondand the third regions, and the polarization direction in the first andthe third regions may be changed while recording the polarizationdirection.

In an example embodiment of the invention, when reading the two data,data “1” and “1” may be read when the drain current is determined to belarger than a first reference current. Data “1” and “0” may be read whenthe drain current is determined to be smaller than the first referencecurrent and larger than a second reference current. Data “0” and “1” maybe read when the drain current is determined to be smaller than thesecond reference current and larger than a third reference current. Data“0” and “0” may be read when the drain current is determined to besmaller than the third reference current.

According to some example embodiments of the invention, theferroelectric memory device having the above-mentioned cell circuits mayhave unit cells, each of which is capable of performing reading/writingoperations for at least two data. Thus, the ferroelectric memory devicemay have a high degree of integration.

The foregoing is illustrative of the present invention and is not to beconstrued as limiting thereof. Although a few example embodiments of thepresent invention have been described, those skilled in the art willreadily appreciate that many modifications are available in the exampleembodiments without materially departing from the novel teachings andadvantages of the present invention. Accordingly, all such modificationsare intended to be included within the scope of the present invention asdefined in the claims. Therefore, it is to be understood that theforegoing is illustrative of the present invention and is not to beconstrued as limited to the specific example embodiments disclosed, andthat modifications to the disclosed example embodiments, as well asother example embodiments, are intended to be included within the scopeof the appended claims. The present invention is defined by thefollowing claims, with equivalents of the claims to be included therein.

1. A stacked ferroelectric memory device comprising: a plurality ofselection transistors on a substrate, wherein each of the selectiontransistors includes a first gate structure, a first impurity region anda second impurity region; a first insulating interlayer covering theselection transistors; a plurality of bit line structures electricallyconnected to the first impurity regions; a second insulating interlayercovering the bit line structures; a plurality of plugs disposed throughthe first and the second insulating interlayers, wherein each of theplugs makes contact with the second impurity region; a plurality ofactive patterns on the plugs and the second insulating interlayer,wherein each of the active patterns makes contact with the plugs; and aplurality of ferroelectric transistors on the active patterns, whereineach of the ferroelectric transistors includes a second gate structure,a third impurity region and a fourth impurity region, and wherein thesecond gate structure includes a ferroelectric layer pattern and aconductive pattern.
 2. The device of claim 1, wherein the plurality ofselection transistors are connected in series and the plurality offerroelectric transistors are connected in series.
 3. The device ofclaim 2, wherein each of the first and the second impurity regionsserves as a common source/drain region of adjacent selection transistorsand each of the third and the fourth impurity regions serves as a commonsource/drain region of adjacent ferroelectric transistors.
 4. The deviceof claim 1, wherein each of the plurality of plugs comprises dopedsingle crystalline silicon.
 5. The device of claim 1, wherein theferroelectric layer pattern and the conductive pattern are sequentiallystacked in each of the second gate structures.
 6. The device of claim 1,wherein each of the plurality of plugs has a height greater than thoseof the bit line structures.
 7. The device of claim 1, wherein each ofthe second gate structures comprises one of ametal-ferroelectric-silicon (MFS) structure, ametal-ferroelectric-metal-silicon (MFMS) structure and ametal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure. 8.The device of claim 1, wherein the third and the fourth impurity regionsare overlapped by side portions of the second gate structure.
 9. Thedevice of claim 8, wherein each of the second gate structures isconfigured to store at least two polarization states.
 10. The device ofclaim 1, wherein a spacer layer and an encapsulating barrier layer (EBL)are stacked on a sidewall of the second gate structure.
 11. The deviceof claim 10, wherein the spacer layer comprises silicon nitride and theEBL comprises aluminum oxide.
 12. The device of claim 1, wherein a fifthimpurity region is disposed in each of the active patterns to connectthe third impurity region to each of the plugs.
 13. The device of claim1, further comprising a plurality of first data line structures, whereineach of the first data line structures is connected to the fourthimpurity region.
 14. The device of claim 1, further comprising a seconddata line structure electrically connected to a channel region of eachof the ferroelectric transistors, wherein the channel region is disposedbetween the third and the fourth impurity regions.
 15. The device ofclaim 1, wherein the substrate includes an active region and anisolation region, and wherein the active region has a linear shapeextending in a first direction.
 16. The device of claim 15, wherein eachof the first gate structures has a linear shape extending in a seconddirection substantially perpendicular to the first direction.
 17. Thedevice of claim 15, wherein each of the active patterns has a linearshape extending in the first direction.
 18. The device of claim 16,wherein each of the second gate structures has a linear shape extendingin the second direction.
 19. A ferroelectric memory circuit comprising:a first string having a plurality of selection transistors each of whichincludes a first gate structure, a first source region and a first drainregion, wherein the selection transistors are connected in series andthe first string extends in a first direction; a plurality of word linesdisposed in a second direction substantially perpendicular to the firstdirection and electrically connected to at least one of the first gatestructures; a plurality of bit lines extending in the first direction,wherein the bit lines are connected to at least one of the first sourceregions; a second string having a plurality of ferroelectric transistorseach of which includes a second gate structure, a second source regionand a second drain region, wherein the ferroelectric transistors areformed on an active pattern to be connected in series and the secondstring extends in a third direction, wherein the second source regionand the second drain region are overlapped by side portions of thesecond gate structure, and wherein the second source region iselectrically connected to a corresponding first drain region; aplurality of plate electrode lines disposed in a fourth directionsubstantially perpendicular to the third direction, wherein the plateelectrode lines are electrically connected to at least one of the secondgate structures; a plurality of first data lines electrically connectedto the second drain region; and a plurality of second data lineselectrically connected to the active pattern.
 20. A method of driving aferroelectric memory device, the method comprising: recording apolarization direction in each of a first region, a second region, and athird region of a second gate structure of a ferroelectric transistor byturning on a selection transistor and applying a predetermined voltageto each of the second gate structure, a second source region and asecond drain region of the ferroelectric transistor, wherein the secondsource region is overlapped by the first region of the second gatestructure, a channel region disposed between the second source regionand the second drain region is overlapped by the second region, and thesecond drain region is overlapped by the third region; and reading twodata from the ferroelectric transistor by turning on the selectiontransistor and measuring a drain current of the ferroelectrictransistor, wherein the drain current varies according to thepolarization direction of each region of the second gate structure. 21.The method of claim 20, wherein recording the polarization directioncomprises: recording substantially the same polarization directions ineach of the first, the second and the third regions; and changing thepolarization direction in the first and the third regions, so that thepolarization directions in the first and the third regions are recordedto be different from that of the second region.
 22. The method of claim20, wherein reading the two data comprises: reading data “1” and “1”when the drain current is determined to be larger than a first referencecurrent; reading data “1” and “0” when the drain current is determinedto be smaller than the first reference current but larger than a secondreference current; reading data “0” and “1” when the drain current isdetermined to be smaller than the second reference current but largerthan a third reference current; and reading data “0” and “0” when thedrain current is determined to be smaller than the third referencecurrent.
 23. The method of claim 20, wherein recording the polarizationdirection comprises: recording substantially the same polarizationdirections in each of the first, the second and the third regions; andchanging the polarization direction in the first region, so that thepolarization direction in the first region is recorded to be differentfrom that of the second and third regions.